Efficient Energy Recovery in 9T Adiabatic SRAM Cell Using Body Bias
نویسندگان
چکیده
Power dissipation is one of the major concerns of Very Large Scale Integration (VLSI) circuit designs. Leakage power is becoming the dominant power component in deep submicron technology. In this work a new 9T adiabatic SRAM is presented. The elementary cell structure of adiabatic SRAM consists of two high load resistors which are constructed of PMOS, a cross-coupled NMOS pair, NMOS switch which is necessary to restrict short circuit current and two trapezoidal-wave pulses. It has been shown that the energy consumption of the adiabatic circuit is lower than that of conventional SRAM. In the proposed SRAM cell, in order to further reduce the subthreshold leakage current and average power dissipation, optimum bulk bias is used. From the simulation results, it has been shown that the energy is efficiently recoverd using adiabatic charging and body bias. The simulation is carried out at 180nm technology.
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Design and Analysis of Power Efficient 9t Adiabatic Sram Cell
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